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«Сезам». Оживляем домофон на одного абонента
Приветствую всех!
На прошлой неделе я рассказывал про такой артефакт как домофон "Сезам" с тремя ручками. Тогда нам удалось успешно разобраться с его работой и запустить позднюю версию платы.
Сегодня мы продолжим всю эту тему: оживим раннюю плату, подключим абонентское устройство и заставим работать домофон на одного абонента. Как водится, будет много интересного.
Читать дальше →BML Designing RISC-V SoCs with FPGAs : Part-Femto-CPU Memory Access
2025.09.07 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent my 30+ year career designing embedded systems using ASICs, FPGAs, and embedded CPUs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here.
The previous chapter introduced a very simple CPU core capable of executing only 3 of 47 RISC-V machine code instructions. Those three are just enough to increment a 32 bit register in a loop. This chapter enhances femto_cpu.v to include bus read and write access and provides an example of mapping...
Black Mesa Labs
BML Designing RISC-V SoCs with FPGAs : Part-Femto-CPU Counter
2025.09.06 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent my 30+ year career designing embedded systems using ASICs, FPGAs, and embedded CPUs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here.
The previous chapter explained RISC-V assembly language and machine code. This chapter introduces a very simple CPU core which is capable of executing only 3 of 47 RISC-V machine code instructions. Those three are just enough to increment a 32 bit register in a loop. Eventually this “Femto-CPU” will flash a...
Black Mesa Labs
A Navajo weaving of an integrated circuit: the 555 timer
The noted Diné (Navajo) weaver Marilou Schultz recently completed an intricate weaving composed of thick white lines on a black background, punctuated with reddish-orange diamonds. Although this striking rug may appear abstract, it shows the internal circuitry of a tiny silicon chip known as the 555 timer. This chip has hundreds of applications in everything from a sound generator to a windshield wiper controller. At one point, the 555 was the world's best-selling integrated circuit with billions sold. But how did the chip get turned into a rug?
"Popular Chip" by Marilou Schultz. Photo courtesy of First American Art Magazine.The 555 chip is constructed from a tiny flake of...
Легендарный вакуумный триод 1920-х — ТМ. История, конструкция, характеристики
Электровакуумные приборы (ЭВП) интересны сами по себе — это подтверждает и нынешняя мода на «ламповый звук» и радио, хотя, казалось бы, во времена нейросетей и частных космических полётов хрупкие и прожорливые стеклянные приборы, за исключением нескольких очень специфичных применений, давно пора позабыть. В тлеющих оранжевым накалах, однако, ищут и находят и ностальгию, и тепло, и некую душевность. Отдельная область бытия — ЭВП как любительское техническое творчество. В самом деле — технология изготовления, например, несложного вакуумного триода сравнительно легко воспроизводима в кустарных и даже домашних условиях, и исторически первые промышленные радиолампы могут здесь дать массу полезных сведений в силу простого своего устройства...
HackRF Pro Production Timeline Update
Since our June announcement, we’ve made substantial progress toward the HackRF Pro launch, and we’d like to share an update on the project timeline.
Progress So Far:
All of the production parts that we expected to have a long lead time (which were ordered months in advance of our initial announcement in June) have been delivered to our contract manufacturer. We completed two additional hardware revisions to improve RF performance. We are now on HackRF Pro r1.1.1, which we anticipate will be the final revision. If there are further changes, they will be minor and will not include a PCB layout change. We delivered...«Сезам». Оживляем раритетный домофон с тремя ручками
Приветствую всех!
Неделю назад я уже рассказывал про такой артефакт из конца восьмидесятых как домофон «Сезам». Однако тогда ограничился лишь тем, что рассказал их историю и показал устройство панели и абонентского блока.
Читать дальше →BML Designing RISC-V SoCs with FPGAs : Part-RISC-V Assembly Language
2025.09.01 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent the majority of my 30+ year career designing digital logic circuits in ASICs and FPGAs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here.
This chapter explains RISC-V assembly language. With Bare-Metal SoC development, a minimal amount of assembly language knowledge is required.
CPUs, for the most part, don’t execute software programming languages like C or even assembly language. CPUs execute machine code, the lowest-level form of software instructions—a sequence of binary or hexadecimal...
Black Mesa Labs
BML Designing RISC-V SoCs with FPGAs : Part-GNU Cross-Compiler
2025.08.31 : I’m Kevin Hubbard, Electrical Engineer. I’ve spent the majority of my 30+ year career designing digital logic circuits in ASICs and FPGAs. It’s been an amazing journey that I hope others will pursue. I’m giving back now in writing this “BML Designing RISC-V SoCs with FPGAs” series which starts here.
This chapter explains installing and using the GNU GCC Cross-Compiler tool-chain for compile bare-metal C code into RISC-V machine code.
At the beginning of time, CPUs were programmed in assembly language. Assembly is fine for small projects, and was easy enough to learn back in the 8-bit 6502 and Z-80...
Black Mesa Labs
BML Designing RISC-V SoCs with FPGAs : Part-Intro
Table of Contents:
Part-1 : What are SoCs?
Part-2 : History of Modern Computer Architecture
Part-3 : RISC-V Assembly Language
Part-4 : RISC-V and the Femto core
Part-5 : Femto-CPU Memory Access
Part-6 : Femto-CPU Blinky in C
Part-7 : GNU cross-compiler
Part-8 : RISC-V and the KianV core
Part-9 : RISC-V and the Hazard3 core
Part-10 : Segger JTAG Debugger
Part-11 : Example Design – LED Blinky
Part-12: Example Design – UART Communications
Part-13 : Example Design – SPI Communications
Part-14 : Example Design – PWM Servo Controller
Part-15 : Example Design – VGA Graphics Controller
Part-16 : ? FreeRTOS ?
2025.08.31 : I’m Kevin Hubbard, BSEE. I’ve been designing with CPUs and digital logic for...
Black Mesa Labs