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GSoC23 — Workweek 13
Introduction
This week I managed to add support for annotating interconnection delays of input/output vectors. What this means for you and your design you will see down below!
As the end of the project approaches, I am going to talk about the final steps to conclude this project.
SDF: Interconnection delays for input/output vectorsTwo weeks ago, I announced that I had implemented interconnection delays in iverilog! If you have had a closer look (or read the summary), you know that there was still a big limitation: only scalar input/output ports could be annotated.
That means if you have a nice 32-bit RISC-V CPU and...
Linkdump: August 2023
Free Stuff - July 2023
The July recipient for the Great Scott Gadgets Free Stuff Program is Joona. Joona plans to use the YARD Stick One we are sending him to develop and test radios. He will be writing documentation and creating tutorials on his projects.
GSoC23 — Workweek 12
Taking a Break
As announced last week, I took a break from programming to enjoy the summer. Now I am back with renewed energy and will continue my work next week. My priority is to implement support for annotating interconnection delays of input/output vectors.
You will hear from me next week!
GSoC23 — Workweek 11
Introduction
Finally, the time has come! I was able to correctly simulate all interconnection delays for the example designs I created. You can find out how I did it and what happens next in this blog post - so read on.
Incorrect annotationThere was a slight bug in the intermodpath annotation code I wrote. When an output of a module was connected to more than one module inputs with different interconnection delays, this caused under certain circumstances the delay to be the same for all paths.
Fixing this bug pushed the success ratio for both example designs to almost 100% - almost. Now...
August Update: Kept You Waiting, Huh?
We apologize for the lack of regular community updates during the past few months. In short, the people who usually wrote them became very busy. However, we have a new way to write and publish these updates, involving you: the community.
Quick update: What’s going on?
Welcome to our long-awaited community post, where we aim to address the most commonly asked question while also unveiling some more news. Let’s get started!
Why hasn’t there been a community update for the past few months? Is PINE64 dead?As you may have noticed, there haven’t been any community updates as of late, and we are sorry for the prolonged silence. This isn’t because the community hasn’t been busy, quite the opposite is true. Instead, the problem is that the usual community update authors are too busy with their daily jobs and other tasks around the community. Although thanks to some community...
GSoC23 — Workweek 10
Introduction
This week I have for you a bug hunt of the special kind: Modpath delays enabled by themselves work, interconnection delays as well, but when enabled together together, the modpath delays are ignored.
And as the second topic this week, I'd like to present the interconnect test suite to track the progress of my work on this feature.
Modpath issueI was trying to enable both interconnection delays and specify paths at the same time when I noticed that the modpath delays annotated by the specify blocks suddenly did not work anymore.
After some troubleshooting, it turned out that this issue surfaces when a...
Cynthion Delivery Timeline Update
Note: This is a crosspost of a Cynthion update on Crowd Supply: https://www.crowdsupply.com/great-scott-gadgets/cynthion/updates/cynthion-delivery-timeline-update
Hello, campaign backers and other supporters of Cynthion and Great Scott Gadgets! In this update, we hoped to tell you that manufacturing was in progress and that we were getting close to delivering the first Cynthions to you. Unfortunately, we have encountered more delays while getting the hardware ready to go to manufacturing.
The first delay was caused by another component availability barrier, which is now solved. After our last hardware update, we placed an order with our contract manufacturer for the additional components added to the Cynthion hardware...
GSoC23 — Workweek 9
Introduction
As a reminder, last time I wrote about the issue when multiple functors are connected to a single source. In that case it is unclear to which of the functors the interconnect path must be annotated.
This week I have spent some time in VVP to find out how to add input and output buffers to modules, so that this ambiguity can be solved.
I was also writing smaller tests to make sure that the implementation I am working on is functioning correctly, and to find out what situations are not annotated correctly.
VVPMy goal is to add input and output buffers to...