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Tracing the Line: the art of drawing machines and pen plotters
Tracing the Line is a book of plotter art available for preorder now, coming out this November. Many of our featured artists are included in the book, and AxiDraw makes several appearances in the video teaser. Looks like it will be fantastic!
IDE для разработки на AVR (GCC и Rat)
Раньше для разработки на Си вообще, и под микроконтроллеры AVR в частности я использовал IDE NetBeans, относительно уникальной фичей которой была поддержка С/С++ и GCC-ассемблера из коробки, с подсветкой синтаксис, возможностью сборки проекта и рефакторинга. Но, увы, после того как Oracle передали NetBeans в Apache, те превратили эту некогда неплохую IDE в унылое говно, выпилив оттуда поддержку С/С++ и заменив её на непонятное нечно, которое как бы есть (в меню создать С/++ проект все ещё можно), но по факту уже много лет как абсолютно неработоспособно.
В итоге пришлось искать альтернативу для разработки на...
Как понять сколько дать памяти задаче во FreeRTOS. Распределение памяти. Отладочные функции
Вообще тема довольно обширная и тут есть множество разных методик, принципов. Да еще FreeRTOS поддерживает кучу разных методов организации памяти. Я предпочитаю использовать кооперативный режим без вытеснения (задачи передают управление сами) и модель кучи heap_1.c, в которой все создается один раз и не удаляется. Поэтому нет фрагментации. Влезает потенциально меньше, зато меньше нежданчиков, когда формально память есть, а выделить ее не получается. И случается это после дождичка в четверг на полную луну.
В этом случае приходится тщательней оценивать аппетиты задачи, чтобы выделить ей ресурсов столько сколько нужно. Что особенно важно, когда задач много.
В двух словах у нас память...
GSoC23 — Workweek 14
Introduction
Hello everybody!
The PR implementing interconnection delays for input/output vectors has been merged! #994
This means that SDF INTERCONNECT support in Icarus Verilog is slowly, but surely becoming actually useful. What better way to celebrate this occasion than to simulate something big? Let's say a RISC-V CPU - the PicoRV32 in default configuration.
Simulating a RISC-V CPU with interconnection delaysI chose the PicoRV32 because it is a well designed CPU written in Verilog and I had already prior experience with it. By default it is configured as RV32I but can be adapted to support various requirements. It is optimized for size and fmax,...
GSoC23 — Workweek 13
Introduction
This week I managed to add support for annotating interconnection delays of input/output vectors. What this means for you and your design you will see down below!
As the end of the project approaches, I am going to talk about the final steps to conclude this project.
SDF: Interconnection delays for input/output vectorsTwo weeks ago, I announced that I had implemented interconnection delays in iverilog! If you have had a closer look (or read the summary), you know that there was still a big limitation: only scalar input/output ports could be annotated.
That means if you have a nice 32-bit RISC-V CPU and...
Linkdump: August 2023
Free Stuff - July 2023
The July recipient for the Great Scott Gadgets Free Stuff Program is Joona. Joona plans to use the YARD Stick One we are sending him to develop and test radios. He will be writing documentation and creating tutorials on his projects.
GSoC23 — Workweek 12
Taking a Break
As announced last week, I took a break from programming to enjoy the summer. Now I am back with renewed energy and will continue my work next week. My priority is to implement support for annotating interconnection delays of input/output vectors.
You will hear from me next week!
GSoC23 — Workweek 11
Introduction
Finally, the time has come! I was able to correctly simulate all interconnection delays for the example designs I created. You can find out how I did it and what happens next in this blog post - so read on.
Incorrect annotationThere was a slight bug in the intermodpath annotation code I wrote. When an output of a module was connected to more than one module inputs with different interconnection delays, this caused under certain circumstances the delay to be the same for all paths.
Fixing this bug pushed the success ratio for both example designs to almost 100% - almost. Now...
August Update: Kept You Waiting, Huh?
We apologize for the lack of regular community updates during the past few months. In short, the people who usually wrote them became very busy. However, we have a new way to write and publish these updates, involving you: the community.