Как понять сколько дать памяти задаче во FreeRTOS. Распределение памяти. Отладочные функции

Вообще тема довольно обширная и тут есть множество разных методик, принципов. Да еще FreeRTOS поддерживает кучу разных методов организации памяти. Я предпочитаю использовать кооперативный режим без вытеснения (задачи передают управление сами) и модель кучи heap_1.c, в которой все создается один раз и не удаляется. Поэтому нет фрагментации. Влезает потенциально меньше, зато меньше нежданчиков, когда формально память есть, а выделить ее не получается. И случается это после дождичка в четверг на полную луну.

В этом случае приходится тщательней оценивать аппетиты задачи, чтобы выделить ей ресурсов столько сколько нужно. Что особенно важно, когда задач много.

В двух словах у нас память...

Электроника для всех

Posted at 2023-09-09 17:01:21 | Electronics | read on

GSoC23 — Workweek 14

Introduction

Hello everybody!

The PR implementing interconnection delays for input/output vectors has been merged! #994

This means that SDF INTERCONNECT support in Icarus Verilog is slowly, but surely becoming actually useful. What better way to celebrate this occasion than to simulate something big? Let's say a RISC-V CPU - the PicoRV32 in default configuration.

Simulating a RISC-V CPU with interconnection delays

I chose the PicoRV32 because it is a well designed CPU written in Verilog and I had already prior experience with it. By default it is configured as RV32I but can be adapted to support various requirements. It is optimized for size and fmax,...

Leos Blog

Posted at 2023-09-07 22:00:00 | Electronics | read on

GSoC23 — Workweek 13

Introduction

This week I managed to add support for annotating interconnection delays of input/output vectors. What this means for you and your design you will see down below!

As the end of the project approaches, I am going to talk about the final steps to conclude this project.

SDF: Interconnection delays for input/output vectors

Two weeks ago, I announced that I had implemented interconnection delays in iverilog! If you have had a closer look (or read the summary), you know that there was still a big limitation: only scalar input/output ports could be annotated.

That means if you have a nice 32-bit RISC-V CPU and...

Leos Blog

Posted at 2023-08-31 22:00:00 | Electronics | read on

Linkdump: August 2023

Space Elevator (Also, from the same site: Password game) The Amazing Story of How Philly Cheesesteaks Became Huge in Lahore, Pakistan Early computer art in the 50’s & 60’s Maryland License Plates Advertising Filipino Casino My Benihana, Myself How much does animation cost? A price guide Cats apparently recognize their names A rubber block that can count SmarterEveryDay takes a tour of a Progressive die stamping facility (YouTube) From back in 2018: DOOMBA: Automatically generate DOOM level maps for your house from Roomba tracking data The mystery of the Bloomfield bridge

Evil Mad Scientist Laboratories

Posted at 2023-08-31 16:01:01 | Electronics | read on

Free Stuff - July 2023

The July recipient for the Great Scott Gadgets Free Stuff Program is Joona. Joona plans to use the YARD Stick One we are sending him to develop and test radios. He will be writing documentation and creating tutorials on his projects.

Great Scott Gadgets

Posted at 2023-08-30 12:00:00 | Electronics | read on

GSoC23 — Workweek 12

Taking a Break

As announced last week, I took a break from programming to enjoy the summer. Now I am back with renewed energy and will continue my work next week. My priority is to implement support for annotating interconnection delays of input/output vectors.

You will hear from me next week!

Leos Blog

Posted at 2023-08-24 22:00:00 | Electronics | read on

GSoC23 — Workweek 11

Introduction

Finally, the time has come! I was able to correctly simulate all interconnection delays for the example designs I created. You can find out how I did it and what happens next in this blog post - so read on.

Incorrect annotation

There was a slight bug in the intermodpath annotation code I wrote. When an output of a module was connected to more than one module inputs with different interconnection delays, this caused under certain circumstances the delay to be the same for all paths.

Fixing this bug pushed the success ratio for both example designs to almost 100% - almost. Now...

Leos Blog

Posted at 2023-08-17 22:00:00 | Electronics | read on

August Update: Kept You Waiting, Huh?

We apologize for the lack of regular community updates during the past few months. In short, the people who usually wrote them became very busy. However, we have a new way to write and publish these updates, involving you: the community.

PINE64

Posted at 2023-08-15 00:00:00 | Electronics | read on

Quick update: What’s going on?

Welcome to our long-awaited community post, where we aim to address the most commonly asked question while also unveiling some more news. Let’s get started! Why hasn’t there been a community update for the past few months?

PINE64

Posted at 2023-08-12 00:00:00 | Electronics | read on

GSoC23 — Workweek 10

Introduction

This week I have for you a bug hunt of the special kind: Modpath delays enabled by themselves work, interconnection delays as well, but when enabled together together, the modpath delays are ignored.

And as the second topic this week, I'd like to present the interconnect test suite to track the progress of my work on this feature.

Modpath issue

I was trying to enable both interconnection delays and specify paths at the same time when I noticed that the modpath delays annotated by the specify blocks suddenly did not work anymore.

After some troubleshooting, it turned out that this issue surfaces when a...

Leos Blog

Posted at 2023-08-10 22:00:00 | Electronics | read on