GSoC23 — Workweek 12

Taking a Break

As announced last week, I took a break from programming to enjoy the summer. Now I am back with renewed energy and will continue my work next week. My priority is to implement support for annotating interconnection delays of input/output vectors.

You will hear from me next week!

GSoC23 — Workweek 11

Introduction

Finally, the time has come! I was able to correctly simulate all interconnection delays for the example designs I created. You can find out how I did it and what happens next in this blog post - so read on.

There was a slight bug in the intermodpath annotation code I wrote. When an output of a module was connected to more than one module inputs with different interconnection delays, this caused under certain circumstances the delay to be the same for all paths.

Fixing this bug pushed the success ratio for both example designs to almost 100% - almost. Now...

August Update: Kept You Waiting, Huh?

We apologize for the lack of regular community updates during the past few months. In short, the people who usually wrote them became very busy. However, we have a new way to write and publish these updates, involving you: the community.

Quick update: What’s going on?

Welcome to our long-awaited community post, where we aim to address the most commonly asked question while also unveiling some more news. Let’s get started! Why hasn’t there been a community update for the past few months?

GSoC23 — Workweek 10

Introduction

This week I have for you a bug hunt of the special kind: Modpath delays enabled by themselves work, interconnection delays as well, but when enabled together together, the modpath delays are ignored.

And as the second topic this week, I'd like to present the interconnect test suite to track the progress of my work on this feature.

I was trying to enable both interconnection delays and specify paths at the same time when I noticed that the modpath delays annotated by the specify blocks suddenly did not work anymore.

After some troubleshooting, it turned out that this issue surfaces when a...

Cynthion Delivery Timeline Update

Note: This is a crosspost of a Cynthion update on Crowd Supply: https://www.crowdsupply.com/great-scott-gadgets/cynthion/updates/cynthion-delivery-timeline-update

Hello, campaign backers and other supporters of Cynthion and Great Scott Gadgets! In this update, we hoped to tell you that manufacturing was in progress and that we were getting close to delivering the first Cynthions to you. Unfortunately, we have encountered more delays while getting the hardware ready to go to manufacturing.

The first delay was caused by another component availability barrier, which is now solved. After our last hardware update, we placed an order with our contract manufacturer for the additional components added to the Cynthion hardware...

GSoC23 — Workweek 9

Introduction

As a reminder, last time I wrote about the issue when multiple functors are connected to a single source. In that case it is unclear to which of the functors the interconnect path must be annotated.

This week I have spent some time in VVP to find out how to add input and output buffers to modules, so that this ambiguity can be solved.

I was also writing smaller tests to make sure that the implementation I am working on is functioning correctly, and to find out what situations are not annotated correctly.

My goal is to add input and output buffers to...

GSoC23 — Workweek 8

Introduction

I am currently in the middle of implementing the SDF INTERCONNECT feature and while there was fast progress early on things have now stalled.

What is the issue? Let me explain this by showing you how I intended to annotate the design.

We start at the VPI side, where $sdf_annotate is called to start the process of SDF annotation. Once a INTERCONNECT token is parsed, we call sdf_interconnect_delays with the appropriate parameters.

(INTERCONNECT A0 input1.A (0.014:0.014:0.014) (0.006:0.006:0.006))

(An example of an interconnect annotation)

This function finds the port handles in the respective scopes and requests an intermodpath via vpi_handle_multi and the ports as...

GSoC23 — Workweek 7

Introduction

It's been a versatile week with a lot of stuff going on. Let's see what we got.

To begin with, the PR to handle delayed signals in timing checks as assignments has been merged at the start of the week (PR #966).

This is great because it means if timing checks like $setuphold or $recrem are used in standard cells, the delayed signals are now correctly connected. This is important for SKY130, because until now the outputs of flip-flops and latches were just left unconnected in...

Free Stuff - June 2023

The June recipient for the Great Scott Gadgets Free Stuff Program is Daniel. Dan is planning to use the HackRF One we are sending him to run workshops in his school and with his amateur radio group. He will also be creating videos with his new HackRF One on his YouTube channel “Radio Dan ZL2DTL”. Please welcome Radio Dan to the software-defined radio community!